1. Technical Field
The present disclosure relates to high-speed latches and high-speed dividers.
2. Background Information
High-speed dividers are often realized using two latches that are interconnected in a cascaded configuration, with the two latches being clocked on opposite phases of the incoming clock signal, and with the signals output from the second latch being inverted and fed back to the inputs of the first latch. The two latches can be implemented in different ways. Current Mode Logic (CML) latches are fast, but such a latch generally has four branches, any one of which can conduct current from a supply voltage conductor to ground potential on a ground conductor. Due to the CML topology, there is always current flow from the supply voltage conductor through pullup resistors to the ground conductor through one of the four branches. As a result, current consumption of a high frequency divider implemented using CML latches is undesirably high. Also, the voltage swing of the output signals are generally not rail-to-rail. A so-called pseudo-CML latch can therefore be used. One such pseudo-CML latch is set forth in U.S. Patent Publication No. US2009/0284288A1. The pseudo-CML latch results in the divider having reduced current consumption.